Integrated Design Ecosystem for Chiplets Heterogeneous Integration and Chip-to-Chip Interconnects in Advanced Packaging Technology

As chiplets containing multiple diverse functional dies are integrated into a single package, the demand for advanced packages with higher density interconnects and larger footprint body sizes has surged. However, the inherent complexity and dense connectivity of these advanced packages present significant challenges when employing traditional Electronic Design Automation (EDA) tools for packaging design and assembly manufacturing validation. Moreover, as chiplet-based designs transition from single monolithic die to multi-chiplet configurations, effectively planning, managing, and optimizing the top-level design and connectivity to achieve optimal performance, power, and area (PPA) among the chiplets becomes increasingly challenging and complicated compared to the traditional approach of separately planning and executing IC and package layout designs. Furthermore, the design of interconnect interfaces and protocols among chiplets is also very crucial. These designs must align with performance expectation, manufacturing processes, and system integration requirements while ensuring interoperability and maintaining a balance between performance and flexibility. Additionally, different application domains require distinct interconnect interfaces, often with conflicting performance indices such as transmission bandwidth, latency, and power consumption. Especially, the use of die-to-die interconnects for chiplets integration often takes the proprietary links from different customers, thus creating design boundaries and limiting the widespread adoption of advanced packaging technology and chiplets from various suppliers. Therefore, the development of new system-level design methodologies and design ecosystem are required.In this paper, we introduce a novel Integrated Design Ecosystem (IDE) to enhance design flexibility across various advanced packaging technologies including 2.5D Si TSV and High Density Fanout (HD FO) Redistribution Layer (RDL), while accommodating diverse customer design systems. The IDE has demonstrated a significant 50% improvement in design cycle time by seamlessly integrating IC design tool with package design tools. It also addresses design-for manufacturing (DFM) validation and electrical performance considerations. Additionally, we outline the design considerations and specifications for interconnect interfaces by leveraging the Universal Chiplet Interconnect Express (UCIe) standard. A comparative analysis is conducted using advanced x32 and x64 UCIe standards within the context of advanced High-Density Fanout Chip-on-Substrate (FOCoS) packaging technology. The results demonstrate that achieving higher performance with x64 need more complex RDL signal routing with significantly smaller RDL land/space (L/S) down to 1.7/1.7um, compared to x32 with RDL L/S of 2/2um while maintaining the consistent transmission speed of 32Gbps. Finally, an advanced mechanical analysis workflow for chiplet-based design is proposed and the turnkey toolbox is also presented. This comprehensive toolbox encompasses the designs of RDL interposer and package, electrical performance modeling and simulation, mechanical and thermal stress analysis, material selection, and reliability testing in assembly production.