Performance Evaluation of UCIe-based Die-to-Die Interface on Low-Cost 2D Packaging Technology

With die sizes reaching reticle limits and a persistent increase in the cost of advanced technology nodes, heterogeneous integration and chiplet-based designs are gaining exponential traction. Die-to-die interconnects are an integral part of chiplet-based systems and are a subject of innovation and optimization for high-performance applications. Designing a die-to-die interface in an appropriate packaging architecture while adhering to industry standards is key to maximizing the benefits of a chiplet-based system. SerDes-based interconnects and parallel interfaces are commonly used for chiplet communication in standard and advanced packages respectively. Due to additional assembly and process steps, advanced packaging technologies are much costlier than standard 2D packaging technologies. This paper demonstrates a parallel interface in a standard 2D package, a cost-optimized alternative, while providing moderate power and beachfront efficiency. The interface is designed in compliance with the standard package option of UCIe, which is an emerging industry standard for die-to-die interfaces. The package layout design was done to achieve a total wiring density of ~70 wires/mm. The design is observed to be close to voltage transfer function loss compliant at various distances up to 25 mm between the UCIe modules. The simulation data is validated by measurement data. This work utilizes analytical cost models to quantify the cost-bandwidth trade-off between chiplet designs in standard 2D and advanced 2.5D packaging. The impact of the technology node of the chips and the different 2.5D options available in the market on the cost analysis framework is also explored.