A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems

In recent years, the open-source RISC-V Instruction Set Architecture (ISA) has proven to be a strong competitor to the long-established ARM architectures. Following this development, it is therefore of high interest to have a clear and comprehensive understanding of how RISC-V compares to ARM. So far, existing literature focuses more on comparing specific aspects of RISC-V and ARM processors, such as performance, energy efficiency, or code size. However, none of the available studies take a holistic approach and compare the ISAs themselves. This paper aims at an in-depth analysis and comparison of two specific ISAs suited for embedded systems. More precisely, the subset of the Thumb instruction set supported by the ARM Cortex-M0+ processor and RISC-V’s RV32IMCZcZicsr instruction set. Our comparison covers the following aspects: first, the programmer’s level and encoding formats. A key difference is that ARM and RISC-V focus on different constraints inherent with embedded systems: ARM on compression to achieve a smaller memory footprint and RISC-V on regular formats to simplify the decoding which can reduce the area requirements of the core. Second, the individual instruction sets. Both ISAs provide a lot of instructions with similar functionality. However, there are some instructions supported by the ARM Cortex-M0+ that the chosen RISC-V ISA cannot easily replicate. Finally, we provide sequences of RISC-V instructions that can replicate specific Thumb instructions. While RISC-V can emulate all of them, it can’t perform them as efficiently as ARM as it needs more instructions to provide the same functionality.