In-Depth DTCO Analysis on Scaling Gate-All-Around Nanosheets/Nanowires for 20 Å Node and Beyond Technologies

In this article, the dc and ac performances of gate-all-around (GAA) field-effect transistors (FETs) are studied targeting the 2-nm node and beyond technologies. Considering the multi-stack nanowire (NW)/nanosheet (NS) devices, the electrostatics, parasitics, currents, and energy-delay parameters are benchmarked. The GAA-NW shows a 10-mV/dec improvement in subthreshold slope (SS) and a 40-mV/V reduction in drain-induced barrier lowering (DIBL) compared to the GAA-NS when measured at a gate length of 10 nm. However, NW loses significant drive current at equal silicon area, as well as has larger parasitics than the NS. A 17-stage ring oscillator (RO) analysis shows that the gate length can be scaled (from 12 to 10 nm) in NS FET with a 22% lower delay (iso-energy) when considered a thinner (4 nm) and taller fin (72 nm). The Sentaurus sprocess, sdevice, and mystic are used to optimize and benchmark these ultrascaled transistors.