Design and Evaluation of FPGA-Optimized Bangladesh Asymmetrical and Symmetrical Five-Term Karatsuba Multipliers

The current demand for efficient multiplication of large integer polynomials in contemporary cryptographic systems is crucial. This work explores the Karatsuba-like multiplication, recognized as one of the most efficient algorithms. Despite its efficiency, this algorithm is often avoided in practice due to the complexity of sub-multiplications during intermediate computation steps. Consequently, efforts have been directed towards implementing asymmetrical and symmetrical five-term Karatsuba Multiplication, denoted as: AFiTKM-I, AFiTKM-II, SFiTKM-I and SFiTKM-II, focusing on speed and hardware utilization. To assess the overall performance of these proposed design methods, the Area-Time-Product (ATP) is calculated and compared with conventional asymmetrical and symmetrical five-term Karatsuba multiplication (CAFiTKM and CSFiTKM) and existing state-of-the-art approaches. Hardware implementations of five FiTKM multiplication architectures were executed using a Virtex-7 FPGA device in the Xilinx ISE platform. Comparing the performance of the best proposed five-term Karatsuba multiplication (AFiTKM-II) based on $\Delta {ATP}$ with other state-of-the-art designs, it is 22.293%, 80.445%, 31.975%, 0.892%, 36.795%, 2.198% and 0.380% better than Direct Multiplication (DM), Traditional Schoolbook Multiplication (Traditional SBM), CAFiKM, AFiKTM-I, CSFiTKM, SFiTKM-I and SFiTKM-II respectively, for 1024-bit inputs.