A Multi-Chiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices

Computing-in-memory (CIM) architectures based on various devices, such as RRAM, SRAM, DRAM, etc., have demonstrated promising energy efficiency. Single-device-based CIM chips show different advantages on performance, power, or area metrics under different workload/operators sizes and application requirements. Some non-idealities, such as the write endurance of some non-volatile devices, also influence the design choices. Motivated by the emerging 2.5D/3D chiplet integration, this work aims to combine the advantages of CIM/storage chips based on different devices, and proposes a design exploration framework to combine the advantages of CIM chips based on these devices in a 3D-stack architecture. This work proposes: 1) An evaluation method for the power, performance, and area metrics of the multi-chiplet CIM architecture; 2) An abstraction for the single-device-based CIM chiplets and AI algorithm operators; and 3) A mapping and optimization strategy to explore the 2.5D/3D CIM chiplet set. The effectiveness of the mapping strategy is verified with a small-scale brute-force search. The proposed design exploration framework can help to find a better multi-chiplet CIM architecture. Under a simple design case, the proposed 3D CIM architecture shows 4.68×-53.32× energy efficiency compared with the single CIM chip baselines. The abstracted chiplet library is open-source available in the open-source link https:// github.com/dai0dai/3D CIM Chiplet Architecture Exploration.