Hardware Design and Implementation of Digital Lock-In Amplifier for Multi-Channel Parallel Impedance Measurement

The current trend is to perform signal processing algorithms in the digital domain, rather than in the analog domain. Thus, field programmable gate arrays (FPGAs) which has advantages in digital signal processing become a common choice for digital implementation of various analog signal processing functional module. However, performing complex algorithms using hardware description languages could be a challenging task. This paper demonstrates the use of high-level synthesis method to implement digital signal processing functions. Through high-level synthesis, some frequently inves-tigated signal processing functions, e.g. the lock-in amplifier, FIR filters, could be conveniently implemented with optimized pipelining performance. Results showed that, the development speed and optimization capability of high-level synthesis method in developing mathematical algorithms has demonstrated great advantages against the common hardware description language implementation. The pipelining optimization has enabled the lock-in amplifier 3 times faster than the common implementation. In addition, it also offers the convenience in accomplish the interface of IP core to the embedded ARM core.