Performance Evaluation of a New Universal Time Domain Gating Algorithm

This paper presents a new Time Domain Gating (TDG) algorithm to de-embed a Device Under Test (DUT). The algorithm uses scattering parameters (S-parameters) from a typical Vector Network Analyzer (VNA) as input data. The approach isolates the signal part belonging to the component under test from interfering elements, thus enabling stand-alone evaluation. Comparing the results with state-of-the-art commercial and open-source approaches validates the algorithm's performance and confirms its superiority in terms of user flexibility and accuracy. It allows continuous measurement and simultaneous de-embedding of a DUT. Furthermore, it features an optional compensation technique that removes unwanted gating effects and can be applied to any gate. Regardless of the manufacturer, the algorithm can be combined with any VNA. Since it was implemented independently of the measurement equipment, it is universally applicable, for example, to locally remote test objects. The comparison with current implementations shows minimal errors for the proposed algorithm. In addition, several ambiguities in commercially available state-of-the-art algorithms can be identified.