VLSI Architecture for Reversible Radix-2 FFT using Modified Carry Select Adder

FT is generally employed to convert the examined signal to frequency domain. FFT is a proficient method to configure discrete DFT. It is a significant method in DSP field that is used for configuring the DFT proficiently. FFT is just a computational algorithm and not another transform. This DFT modification lessens the calculation time. It firmly limits the execution cost on digital computing systems. In FFT the calculation performances has been improved by applying a divide and conquer approach. This methodology depends on decomposition and it breaks the transform as smaller transforms and the final consolidation leads to derive the complete transform. In FFT, the majority calculations can be dispensed by utilizing the symmetry and the periodicity classifications of the fidget factor. The prime merit of FFT is to decrease the number of computations. In this paper, design 8-point, 16-point, 32-point FFT using reversible modified carry select adder (RMCA) and RDKG. RMCA is operating as a adder and RDKG is operate as a sub-tractor. The design is implemented Xilinx 14.5i and calculate slice, LUT and delay.