Design of A High Performance Time-to-Digital Converter with Zero Dead Time on Xilinx FPGA

Nowadays the time-to-digital converters (TDCs) implemented on field programmable gate array (FPGA) can achieve reasonably high measurement resolution and precision. However, some applications also require TDCs without measurement dead time to avoid event missing. In this paper, we propose a new TDC design method that can achieve high measurement precision while achieving zero measurement dead time as well. Using the traditional structure of tapped delay line (TDL) based TDC, the proposed TDC allows consecutive trigger signals flowing into the TDL and makes the encoder capable of capturing all trigger edges with the output of their timestamps. Since there is the inherent “bubble” problem in TDL for high performance implementation, the latched TDL status is first decomposed into sixteen divisions. The trigger edges on the divisions are identified parallel, and then all the trigger signals on the TDL have to be reinstalled to obtain their precise arrival times. The TDC has been implemented on a Xilinx Zynq Ultrascale+ FPGA for performance evaluation. The test results show that the TDC can achieve a resolution of 1.92 ps and a root mean square (RMS) precision better than 3.3 ps. By measuring two trigger signals located within one TDC sampling clock cycle, the TDC can measure them correctly, which means the proposed design method is effective for realizing zero measurement dead time.