Design and Analysis of a Novel Sample and Hold Architecture Based on D-Latch: Performance Evaluation and Comparative Analysis

The Sample and Hold Circuit (SHC) is a crucial component in many analog signal processing systems, responsible for capturing and maintaining the voltage level of an input signal for subsequent processing. In this paper, a novel architecture for a SHC is proposed based on a D-latch and a transmission gate, utilizing a Folded Cascode Op-Amp (FCO) as a buffer. The proposed design aims to improve performance metrics such as speed, setup time (554.115ps) and hold time (6.903ns) at sample rate (1000KS/s), power consumption
$(80.141\mu \mathrm{W}$
, and high accuracy with large input voltage range of 750 mVp-p (62.5% of Supply voltage) and up to 200KHz input frequency. Subsequently, we present the detailed design of our novel SHC architecture based on the D-latch, with incorporating a transmission gate, the circuit achieves efficient switching of the capacitor, facilitating the sampling and holding of the input analog signal with proper Setup time and hold time depending on input frequency and charging capacitor. Additionally, the FCO serves as a buffer, enhancing the overall performance and stability of the SHC. To assess the performance of the proposed architecture, we conducted a rigorous evaluation and comparative analysis considering SNR(59.274dB), SINAD(59.274dB), SFDR(60.046dB), ENOB(9.553bits). The results demonstrate the superiority of our novel architecture, showing improvements in key performance parameters. This complete work was accomplished in Cadence 90nm CMOS Technology.