Power Efficient Hybrid Low-Power Technique for an SRAM cell

In the world of battery driven devices, semiconduc-tor memories (SRAM) plays an important role. In this work, we have designed a novel hybrid low-power technique for an SRAM cell called BB-SKDG (Body-Biased Sleep Keeper and Drain Gating) for SRAM cells in the 90nm technology node. By incorporating body biasing of three transistors (PMOS) in the pull-up network and varying the SKBD terminal voltages for three transistors (NMOS) in the pull-down network, significant reductions in power consumption during write, read, and hold operations are achieved. Experimental results demonstrate a substantial decrease in average power consumption for write and read operations by 82.1 % and 73.3%, respectively, and a 89.7% reduction in static power for hold operations. The approach shows promise for various applications, including battery- powered wireless sensors, implantable healthcare devices, and embedded computers.