An On Chip BIST Architecture for ADC Parameter Testing and Measurement

This paper introduces a ADC BIST mechanism that uses 12-bit SAR ADC and 14-bit R2R DAC technology. This solution has been used for 40nm automotive microcontroller. On - chip method is used for validating SARADC and DAC static parameter. There are two methods to test BIST off-chip and on-chip. Evaluating the parameter i.e., INL, DNL offline using raw data names off-chip method which required some offline calculation to characterize the BIST circuit, whereas on-chip method does not require this kind of extra calculation. In this method parameter evaluate in background using USER_SMILE algorithm and display pass/fail status based on pre-loaded limits of parameter. Solution has been purposed for reducing cost of testing equipment and testing time.