Design and Optimization of Low-Power CMOS Inverter using LECTOR Technique with Cadence

In recent times, Low power CMOS inverters find applications in diverse electronic systems and devices where energy efficiency is paramount. CMOS inverters are extensively used in portable electronics, such as smartphones, tablets, and wearables, to extend battery life and improve overall efficiency. Various simulation had performed to evaluate different design options and identify the optimal configuration. The LECTOR technique (optimization process) involves adjusting key parameters such as transistor sizing, threshold voltages, and load capacitance to achieve the desired power efficiency while meeting specified performance constraints. The accuracy provided by the LECTOR technique is 99%. This method is implemented in cadence virtuoso.