A Low Voltage and Low Power Analog Multiplier

In this research work, a low voltage analog multiplier has been realized through the utilization of a flipped voltage follower (FVF). The multiplier is characterized by its capacity to function at low power while exhibiting high gain. The exclusive use of transistors in its implementation renders it highly appropriate for fully integrated circuit applications. The multiplier has been developed using a supply voltage of 500 mV and an operating frequency of 25 KHz. The design consumes power of 8.23 uW. Moreover, a comparative study between the proposed multiplier and the conventional gilbert multiplier is presented in the paper. All simulations and layout designs have been conducted through the virtuoso analog design environment (ADE) of Cadence at 45 nm CMOS technology.