A Low-Complexity Design for Complex Multiplication Using Radix-4 Booth Encoding

In this paper, we present a novel design strategy for complex-number multiplication where the real part, as well as the imaginary part, are considered as a 2-point inner-product, and those inner-products are computed by radix-4 modified Booth-encoded distributed arithmetic approach where the partial inner products are reduced by the carry-save reduction process. Reduction of area complexity is achieved by sharing of Booth encoders by the pair of inner-product units. Time complexity is reduced by avoiding the vector-merging adder, which conventionally follows the carry-save reduction of partial products. The post-layout synthesis results using Cadence Innovus with a GPDK 90nm technology library and FPGA synthesis show that the proposed complex multiplier offers significant advantages in area-delay product and energy consumption over the real-number multiplier-based reference architecture.