Pulsed Latch Based Pipelined LFSR for Cybersecurity Applications

This paper proposes a novel power-efficient pulsed latch-based pipelined architecture for 16-bit and 32-bit Linear Feedback Shift Registers (LFSRs). Compared to traditional flip-flop-based implementations that use two storage elements, the pulsed latch implementation uses only one storage element. This approach reduces area and power consumption in pulsed latch-based shift registers. They occupy a lesser area than the flip-flop-based shift registers and also show reduced power consumption. Leveraging this advantage, a novel pipelined LFSR architecture is proposed that showcases a 63% reduction in power consumption, making it a compelling alternative. It also increases the linear complexity and exhibits enhanced randomness, which opens doors for applications requiring high-quality random sequences, such as cryptography and secure communication protocols. The proposed design paves the way for more efficient and robust LFSR implementation with broader real-world applications.