FPGA Realization of High-Efficient Address Generator Algorithm for WiMAX Deinterleaver

Utilizing the Xilinx Field Programmable Gate Array (FPGA), an innovative technique and low-complexity is proposed to efficiently realize the address generation circuitry of the 2D deinterleaver used in the WiMAX trans receiver. The IEEE 802.16e standard is very difficult to realize in FPGA as the floor function associated with the execution of the steps, essential for the variation of the incoming bit stream in medium interleaver/deinterleaver. To eliminates the necessity of floor function and thereby allows low-complexity FPGA implementation is done by the simple algorithm along with its mathematical background. This approach to be novel and highly efficient when compared with conventional look-up table based approach, because the utilization of an internal multiplier of FPGA, the distribution of resources for quadrature phase-shift keying, 16-quadrature-amplitude modulation, and 64-QAM modulations along with all feasible code rates. The proposed method exhibits significant improvement in the use of FPGA resources.