Advanced Zero-Sequence Current Suppression in P-HIL Testbed With Integration of Feed-Forward Compensation and LADRC

A PWM converter-based power hardware-in-the-loop (P-HIL) testbed offers a rapid and cost-effective solution for prototype testing of high-power converters in electric vehicles and smart grid industries. To simplify the configuration and avoid the need for an additional bidirectional DC supply, the power amplifier (PA) can share the DC-link with the device under test (DUT). However, this leads to a zero-sequence circulating current (ZSCC) between PA and DUT due to the coupling of AC and DC ports. The ZSCC involves low and high frequency content that significantly distorts the three-phase current evaluated in the test. While the high frequency content can be mitigated by using common-mode (CM) filters, the low-frequency content has to be attenuated at a control system level. The use of classic control approaches such as proportional-integral (PI) or proportional-resonant (PR) controllers might lead to a difficult attenuation of the low-frequency ZSCC harmonic content unless high control gains are adopted, increasing the probability of unstable behavior. This paper proposes an enhanced control method, integrating a stand-alone zero-sequence voltage (ZSV) feed-forward (FF) compensation and a linear active disturbance rejection control (LADRC) strategy. This approach not only suppresses the ZSCC flowing through the PWM converters of PA and DUT but also compensates for parameter uncertainties and dynamic ZSCC variations due to power injection change, thereby enhancing the overall system performance. The effectiveness of this combined control strategy is demonstrated through experimental results, highlighting its potential to improve accuracy and reliability in the P-HIL testbed.