A $10\ \mu \mathrm{W}$ Front-End Enabling 200 ps Resolution in High-Efficiency Large Area Monolithic Pixel Sensors

This paper presents a low-power, low-mismatch in-pivel circuit optimized for large area monolithic pixel sensors. The design addresses key challenges by achieving low power consumption
$(\mathbf{12.5}\ \boldsymbol{\mu} \mathbf{W}/\mathbf{channel})$
high detection efficiency with a low Equivalent Noise Charge
$(\mathbf{200}\ \mathbf{e}^{-})$
, and low time jitter (200 ps). An optimized power grid minimizes performance variation across the chip area and mitigates noise injection from dynamic voltage drops. The pixel-to-pixel charge threshold mismatch of
$\mathbf{200}\ \mathbf{rms}\ \mathbf{e}^{-}$
can be further reduced by a factor of 4 through a local 3-bit (DAC) for pixel-level threshold tuning. The circuit is implemented in a
$\mathbf{2.3}\ \mathbf{cm} \times \mathbf{3.0}\ \mathbf{cm}$
monolithic pixel sensor, integrating a matrix of
$\mathbf{132}\times \mathbf{192}$
hexagonal pixels (
$\mathbf{150}\ \boldsymbol{\mu} \mathbf{m}^{2}$
area). It is produced in a 130 nm SiGe BiCMOS process featuring SiGe Heterojunction Bipolar Transistors (HBTs). This sensor is designed for the
$\mathbf{100}\boldsymbol{\mu}\mathbf{PET}$
scanner, enabling high-resolution molecular imaging. It offers significant potential for applications requiring high-efficiency detection in large-scale systems.