Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology

This work proposes and analyzes a split-constant-slope digital-to-time converter topology (SCS DTC). The proposed circuit is extremely robust to the non-linearities of current generators and non-linear capacitors, as well as to process spreads. As a case study, a 11-level SCS DTC with a 20.8 ps LSB and a 208 ps full-scale delay is designed in a 22 nm FDSOI CMOS technology. Simulations show a very small peak-to-peak INL of 59 fs (0.028%), in line with the state of the art.