Design of a Hardware-Efficient Floating-Point Multiplier with Dynamic Segmentation

In this paper, we present a novel low-power floating-point multiplier design that leverages dynamic segmentation to enhance efficiency. Our approach approximates the mantissa product through a simple addition of dynamically extracted input segments, supplemented by an additional correction term implemented through a small, hardwired lookup table. Compared to previous proposals, our FPM shows optimal results in terms of the power-accuracy trade-off, with power savings exceeding 85% compared to an exact implementation. The proposed multiplier offers remarkable performance in image processing applications, with Structural Similarity Index (SSIM) values approaching 1 and Peak Signal-to-Noise Ratio (PSNR) reaching up to 66dB.