A Low Quiescent Current Capacitor-Less LDO Voltage Regulator in 22 nm FDSOI CMOS

This paper presents a low-power, capacitor-less, low-dropout (LDO) voltage regulator fabricated in a 22 nm FDSOI CMOS technology. The proposed LDO design uses a current charge and discharge path compensation circuit that provides a rapid transient response as well as good stability at wide load variations. It draws a quiescent current of 2.5 µA from a single 1.5 V supply voltage. Measurement results show that the LDO provides a stable 0.8 V output voltage up to 20 mA with 0.8 m V
$N$
line regulation and 1.15 m V /mA load regulation. Furthermore, the power supply rejection ratio (PSRR) of 62 dB up to 100 Hz and compact size of 0.04 mm
²
, including a 100 pF load capacitor, makes the proposed LDO design an attractive solution for ultra-low-power applications, e.g., biomedical and sensing interfaces.