A Bit-Line Biasing Circuit for Analog In-Memory Computing Based on Phase Change Memory

Analog In-memory Computing (AIMC) is a promising approach for reducing energy consumption and latency caused by internal data transfers of conventional computing architectures. Phase-change Memory (PCM) is a valuable technology for AIMC due to its multi-bit and high-density data storage capability. The most explored task in AIMC paradigms is Matrix-Vector Multiplication (MVM) and, during the computation, the array of PCM is typically read at fixed voltage. This paper proposes a detailed analysis and experimental characterization along with a comparison with other simulated solutions of a bit line biasing circuit scheme used for applying the reading voltage to an array of embedded PCM. The proposed scheme has been designed and employed in a prototype designed and fabricated in a 90-nm STMicroelectronics CMOS technology aimed at the execution of Multiply and Accumulate (MAC) tasks, which are the core of MVM. Results show that the proposed scheme represents a trade off solution between accuracy and power consumption.