Asynchronous vs Synchronous SAR ADCs – Performance Beyond Nominal Speed

This paper presents a comparison between a Itl-bit asynchronous SAR (ASAR) ADC and a 10-bit synchronous SAR (SSAR) ADC, both designed and simulated in a 22-nm FDSOI CMOS process. To further support the simulation results, the ASAR ADC has also been fabricated and measurements are pre-sented. As opposed to the abrupt SNDR collapse in the SSAR ADC, the SNDR of the ASAR ADC shows a more graceful deg-radation as the sampling frequency is increased beyond the highest nominal. At the same time, the ASAR ADC consumes approximately 20% less power than the SSAR ADC.