A 28-nm CMOS 60-GHz LNA for OOK Low-Power Receivers

This paper presents the design of a 60-GHz low-noise amplifier (LNA) for low-power Gbit/s applications in a 28-nm bulk CMOS technology. The amplifier adopts a two-stage pseudo-differential architecture with integrated input transformer for both electrostatic-discharge (ESD) protection and simultaneous noise/impedance matching at a low current consumption. The design is aimed at best tradeoff among gain, frequency bandwidth and power consumption, while minimizing the noise figure by taking advantage of the impedance transformation ratio provided by the integrated input transformer. The LNA is operated at 0.9 V and achieves a gain of about 19 dB with a 3-dB bandwidth of 6 GHz around 60 GHz. It exhibits a noise figure (NF) of 6.9 dB, also including the input transformer loss, and an input 1-dB compression point (IP
1dB
) of −14 dBm with 8.3-mW power consumption. With an on-off keying (OOK) modulation, the LNA achieves an energy efficiency of less than 3 pJ/bit.