A 4T GC-eDRAM Bitcell with Differential Readout Mechanism For High Performance Applications

Gain-cell embedded DRAM (GC-eDRAM) is a dense, low power option for embedded memory implementation, supporting low supply voltages. However, due to its structure, the readout scheme is slow and requires a high precision external reference voltage to improve performance. In this work, we propose a novel bitcell featuring a differential readout mechanism for high frequency operation without the need for an external voltage supply. A 16 kbit memory macro was implemented in 65nm CMOS bulk technology offering up to 3x improvement in access time compared to standard GC-eDRAM solutions and similar read time to SRAM bitcells, while providing up-to 30% reduction in bitcell area compared to standard SRAM solution.