Analysis and Design of High-Speed, Linear and Fullscale Input Swing Voltage to Time Converters

The output performance of time-based analog to digital converters (ADCs) realized using voltage to time convert-ers (VTCs) is limited due to the nonlinear behaviour of VTC. This work attempts to analyze existing VTC architectures to understand the limitations of VTC design. It further proposes a novel VTC architecture that achieves full-scale input swing and operates at 1 GS/s. The proposed VTC architecture is designed using CMOS 65 nm process and post-layout simulation results are presented to show its efficacy. It achieves 7.3 ENOB while consuming 0.2 mW power. It has a figure of merit of 1.3 fJ/cs-step and an output range of 410 ps.