Sub-100 Ps Modular Asynchronous Readout for Single Event Cluster Detection in Pixel Sensor Applications

This paper presents a modular asynchronous read-out architecture suitable for large pixel detectors, specifically designed for single cluster events reconstruction. The architecture is based on a projection structure to efficiently transmit hits to the periphery using a limited number of lines, resulting in low power consumption and fast-timing performance. The proposed readout architecture has been implemented in a 2.3×3.0 cm
²
ASIC in 130 nm SiGe BiCMOS monolithic technology for a PET scanner. The ASIC dimensions pose significant challenges, particularly in achieving asynchronous readout with high precision. To reconstruct event clusters of maximum dimension 5×5 pixels without ambiguity, the chip has been segmented into modules of 6×6 pixel indexes, 4 quadrants, 11 super-pixels, and 16 super-columns. A skew in the order of 100 ps resulted from the design and layout methodology. While the front-end exhibits a jitter of 200 ps at nominal input charge, simulations demonstrate that the architecture introduces a negligible jitter below 1 ps, with expected mismatch introducing additional skew with
$\sigma= 11$
ps. Additionally, a temperature and voltage variation of 0.6 ps/°C and 7.28 ps/mV respectively are anticipated. The ASIC was submitted for fabrication in October 2023.