Hardware and Software Co-Processing Acceleration Architecture of Range Migration Algorithm for 3-D Millimeter-Wave Imaging

The processing of millimeter-wave synthetic aperture radar (SAR) echo data plays a crucial role in target reconstruction, but it can be computationally time-consuming. To accelerate the reconstruction process, a solution is to leverage field-programmable gate arrays (FPGAs). However, due to the large size of the three-dimensional echo data (ranging from tens to hundreds of megabytes), it cannot be directly cached in the on-chip RAM of the FPGA. Instead, it can be stored in the DDR memory. To efficiently transfer multidimensional arrays from the processing system (PS) to the programmable logic (PL) using AXI-DMA, it is essential to rearrange the dimensions of the arrays. Unfortunately, implementing this operation directly on the FPGA can be challenging. To address this, this paper proposes an algorithm acceleration architecture that combines software and hardware co-processing. The computational part of the imaging algorithm is implemented in the PL section of the ZYNQ 7020 SoC, while the data permutation is performed by the PS.