Monolithic 3D Transposable 3T Embedded DRAM with Back-end-of-line Oxide Channel Transistor

The rising computational demands of artificial intelligence (AI) models are driving increased data transfers from off-chip DRAM, resulting in increased energy consumption and latency. With the conventional Von-Neumann architecture nearing its limits, Near-Memory-Compute (NMC) and In-Memory-Compute (IMC) have emerged as potential alternatives, aiming to minimize memory access by computing directly within memory. The choice between IMC and NMC is contingent on the specific needs of an application, especially when balancing throughput and accuracy. While conventional SRAM is not optimized for extensive parallel computation due to its large footprint, 2T gain-cell (GC) embedded DRAM (eDRAM) presents a favorable alternative. However, its integration with IMC and NMC poses challenges in terms of chip size and data retention. We propose that monolithic three-dimensional (M3D) 3T transposable GC eDRAM with tungsten-doped indium oxide channel (IWO) back-end-of-line (BEOL) transistors to efficiently mitigate these challenges. The benchmark results show that 3T IWO GC eDRAM has 60 % area reduction compared to 10T Si SRAM. Furthermore, the data retention of the proposed design is ~10
⁴
times longer than that of 3T Si GC eDRAM. The comprehensive study from technology to architecture highlights the potential of the 3T IWO GC eDRAM as a robust candidate for L4 cache and parallel computing.