A 1.37 μW, 1.68 μVrms ECG AFE with Embedded DC-Servo Loop, Digital Calibration Unit and Three-State Ripple Reduction Loop

This paper presents a capacitively-coupled chopper instrumentation amplifier designed for the analog front end (AFE) of Electrocardiogram monitoring. It employs an embedded DC-servo loop to reduce the input-referred noise (IRN). Additionally, a digital calibration unit is employed to realize large electrode DC offset (EDO) cancellation ability. To prevent the second harmonic ripple, a three-state ripple reduction loop is proposed here. The proposed AFE is implemented in a 180 nm CMOS process and consumes 1.37 μW from a 1.2 V supply with ±95 mV EDO cancellation range. Besides, the IRN from 1 Hz to 200 Hz is 1.68 μV
rms
with a noise efficiency factor of 4.87.