Reconfigurable Precision SRAM-based Analog In-memory-compute Macro Design

In-memory computing (IMC) is a promising approach for accelerating multiply and accumulate (MAC) operations, which are the primary calculations used in artificial intelligence (AI). The demand for flexible architectures supporting different bit precisions in MAC computations becomes evident. This flexibility balances adapting to specific model requirements and optimizing design performance efficiency. As such, in this paper, we propose a reconfigurable IMC macro design, utilizing 8T static random-access memory (SRAM) bit-cells in 65nm technology, to efficiently perform MAC operations while supporting three bit precisions: 2, 3, and 4 bits for each of the input, weight, and output. The proposed 64×180 macro achieves a normalized peak throughput of 13.82 TOPS, a normalized peak energy efficiency of 291.66 TOPS/W, and a normalized peak area efficiency of 165.98 TOPS/mm
²
.