A Timing Attack Resistant Lightweight Post-Quantum Crypto-Processor for SPHINCS+

SPHINCS+ is a selected hash-based post-quantum cryptography (PQC) for digital signature due to its promised security and simple cryptographic operations. However, the excessive storage requirements and potential side channel attack may be the obstacle in its practical application. In this paper, a compact signature streaming scheme is proposed, saving storage consumption by 88%. Besides, two timing attacks: breakpoint and saving signature attack are presented. These crack critical information for grafting tree attack to carry out a universal forgery. A fake signature compensation protection is designed as their countermeasure with 2×128 bits register and free storage. The lightweight, timing attack resistant processor consumes 5832 LUT, 2794 FF, 1 BRAM, representing lowest/second-lowest consumption in LUT(FF)/BRAM among existing designs, and achieves 1.11×/7.25×/20× area time product (ATP) optimizations in LUT/FF/BRAM.