Back-Gate Coupling Technique for Phase Error Correction in PLL-Based Quadrature VCOs

This paper proposes an approach for reducing the phase error of PLL-based quadrature voltage-controlled oscillators (PLL-QVCOs). The method leverages the back-gate coupling technique to deliberately create a mismatch between the I and Q oscillators that, in effect, reduces or cancels out the effects of unwanted mismatches within the oscillator cores. This technique makes the design more power efficient with a low phase error and phase noise performances simultaneously. It increases the figure of merit (FoM) by 4.7 dB as compared to the conventional design. The proposed PLL-QVCO is designed in a 65-nm CMOS process consuming 5.35 mW from a 0.8 V supply and covers a frequency range of 5.2 to 6.15 GHz. Post-layout simulation results demonstrate phase noise and FoM of -126.1 dBc/Hz and 193.3 dB, respectively, at 1 MHz offset frequency.