Single Slope ADC with Reset Counting for FeFET-based In-Memory Computing

This paper presents the design of a 4-bit Single Slope (SS) ADC adopting reset counting method for current mode in-memory computing (IMC) acceleration in 28nm SLPe technology. Two types of comparators are combined for enhanced power efficiency and lower kickback noise, achieving 50.2 fJ/conv Walden FoM at a reduced area footprint of 101.6 µm
²
. Finally, the SS-ADC is integrated with a 1FeFET1R macro to compute multiply-accumulate (MAC) operations for convolutional or fully connected layers in neural networks. Furthermore, the SS-ADC offers the possibility for higher resolution and the integration of analog non-linear activation function, reducing the digital overhead in neural network accelerators.