Interface Trap Analysis in Multi-Fin FinFET Technology: a Crucial Reliability Issue in Digital Application

This paper focuses on investigating the impact of NBTI degradation on p-FinFETs, a major reliability concern. The impact of donor type interface traps on single and multi-fin FinFET structures are considered for both device and circuit aspects. The degradation of device performance occurs due change in threshold voltage (Vth) and drain current caused by traps. This study extends to analyze the effect of traps on the Voltage Transfer Characteristic (VTC) and transient behavior in an inverter, followed by a study of the Ring Oscillator (RO). We precisely evaluate parameter changes and differentiate the impact among 1-Fin, 2-Fin, and 3-Fin structures. Under NBTI, device reliability concern, the End of Lifetime (EOL) is achieved at a threshold voltage shift of 50 mV, occurring at a trap concentration of 1.25×10
¹²
cm
^-2
. While the change in Vth is consistent across single and multi-fin FinFETs parameters however Subthreshold Slope (SS), transconductance (gm) and DIBL (Drain Induced Barrier Lowering) exhibit more significant variations and degradation, particularly in 2-Fin and 3-Fin structures. In terms of Ring Oscillator (RO) performance, the impact is less pronounced in 1-Fin structures, resulting in finer performance compared to 2-Fin and 3-Fin structures.