A Fast Transient PMOS LDO with AP3 Buffer and Shaped-Hybrid-Bias EA Techniques Achieving 8.15ps FOM

A current-efficient and fast-transient p-type low-dropout regulator (LDO) for high-current load transient in mobile phone applications is presented in this article. A low-power Auxiliary-Path Push-Pull (AP
³
) buffer is employed to provide both high charging and discharging current for gate-capacitance (CgP) of power MOS, hence the undershoot and overshoot performance are optimized simultaneously; Meanwhile the auxiliary path of the buffer further accelerates the transient response. Moreover, the shaped-hybrid-bias circuit accurately control the upper and lower limits of EA’s bias current, by this, maximum LDO’s bandwidth is well controlled and keeps proper margin to the self-resonant frequency of off-chip capacitor, which guarantees good loop stability over wide load range. This circuit has been implemented in a 0.18-µm standard 5V CMOS process and occupies a silicon area of 400 × 250 µm
²
, where 5V devices with a 500-nm minimum channel length are used. With a 1-µF output cap and load steps between 0 A and 270 mA, with 300ns edge time, experimental results show that it features 19/14 mV of undershoot/overshoot at load transient