Modeling and Analysis of Waferscale Switching Network with Multiple System Faults

With the end of Moore's Law and Dennard scaling, waferscale systems that integrate multiple pre-tested known good dies (KGDs) on a waferscale-interposer are new approaches to further improve chiplets-based systems' performance. This paper explores the manufacturing defects of waferscale systems and the effect to network on wafer (NoW). A traffic-balanced routing algorithm is proposed for the irregular network with multiple faults of NoW. The results show that the routing algorithm reduces transmission delay by 57% and improves throughput by 36.4% compared to the normal breadth-first-search algorithm. Besides, we build a throughput model by using the nonlinear least squares method (NLLS) with the parameters of faults number, location and concentration ratio. The results show that the model can reach 0.98 goodness of fit and accurately predict the throughput performance of different irregular NoW topologies. The model can be used to predict the system performance and avoid critical faults of the physical waferscale switching system.