Design Of High-Density Iso-Stable Asymmetric Memory Cell With Upto 10X Reduced Leakage

Embedded memories occupy up to 70% of the die area in modern digital SoCs. Therefore, high-density, low-leakage SRAM cells are desirable. We propose an asymmetrical 4TA SRAM cell and design it and conventional 6T, 5T, and 4T SRAM cells under iso-stable constraints. We show that the proposed 4TA cell is denser by up to 16% and has about 10X lower leakage than the iso-stable conventional 4T cell.