Crosstalk and Power Analysis in Tapered based Composite Cu-CNT TSV in 3D IC

In the recent advancements of 3D integrated circuits, the adoption of tapered-shaped through silicon via (TSV)- bumps emerges as an appealing substitute for conventional cylindrical structure owing to their reduced parasitic effects and space-efficient structure. The copper and carbon nanotube (Cu-CNT) composite based tapered TSV-bump structure offers superior electrical conductivity, thermal stability, and mechanical strength compared to standalone Cu or CNT materials, making them an ideal choice. It is crucial to model the electrical characteristics of Cu-CNT based TSVs-bump, and this can be achieved by employing the effective complex conductivity approach. A comprehensive model, denoted by resistance-inductance-conductance-capacitance (RLGC), is implemented to consider the influences of both the inter-metal dielectric and bump effects. The computation of TSV-bump parasitic is accomplished by applying the current continuity expression, utilizing the partial inductance method, and segmenting infinitesimally thin slices of the bump within a triangular configuration of tube assemblies. In order to validate the proposed model, the quantitative values of TSV-bump parasitics are compared with the EM simulations, revealing a notable conformity with an average deviation of only 2.9%. Further, the crosstalk-induced delay, insertion loss (S21), and reflection loss (S11) for the Cu, CNT, and composite Cu-CNT based tapered TSV-bump structure have been investigated by using a driver-via-load (DVL) in 7nm technology. Furthermore, when compared to the Cu and CNT material, the Cu-CNT composite based tapered TSV-bump depicts an average improvement of crosstalk, insertion, and reflection losses by 39.12%, 48.23% and 57.19%, respectively.