A 12.7 Bit Accurate and 5.3nJ·µV2·ns Comparator with Dynamic-cum-Body Bias Technique in SOI

The paper presents a voltage scalable dynamic-cum-body bias (DB+BB) comparator that uses a degeneration capacitor to prevent complete discharge of the pre-amplifier (pAmp) output nodes. An on-chip controlled bias is provided to the body of input-pair transistors that lowers the threshold voltage, and elongates the charge integration time. It augments the pAmp gain, and reduces the input-referred noise (IRN) and the overall delay. The post-layout simulations in 180nm silicon-on-insulator(SOI) technology demonstrate that the proposed DB+BB pAmp achieves 168.4µV IRN while consuming only 55.52fJ energy per comparison. The proposed comparator achieves a figure-of-merit of 5.3nJ·µV
²
·ns at 100MHz and 1.2V supply.