A Fully Synthesizable Capacitorless Digital LDO for Distributed Power Delivery Network

This paper presents a fully synthesizable capacitorless digital low-dropout regulator (DLDO) for distributed power delivery networks in large-scale digital systems. A coarse-fine dual loop architecture is adopted for better transient response and higher output voltage accuracy. The coarse loop uses a CMP-triggered oscillator to achieve faster recovery under load voltage droop. An inverter-based droop detector is connected directly to the output voltage, which provides rapid detection of undershoot voltage and dispenses with bulky external capacitors. Moreover, the DLDO is implemented using only digital standard cells and auto place-and-route (P&R) tool. The fully synthesizability enables seamless integration into existing digital systems, providing flexibility and scalability. Therefore, the proposed DLDO offers a scalable and portable architecture that has a low design time cost for a distributed power delivery network. The proposed DLDO is implemented and simulated in the 40-nm CMOS technology, with a core area of 0.04 mm
²
. The range of input voltage is from 0.6 to 1.1 V with a 50-mV dropout voltage. When the current load is increased by 120 mA with a 2 ns edge time, the DLDO exhibits a voltage droop of 126 mV, a response time of 2.1 ns and a settle time of 7.5 ns, respectively. The maximum load current and peak current efficiency are 200 mA and 99.98%, respectively.