Novel SRAM based Temporary Memory for PVT Variation Tolerant Analog In-Memory Computing

Analog in-memory computing (IMC) techniques have played a significant role in vastly improving the throughput, energy efficiency, and area of on-chip ML inference engines, breaking through the Von-Neumann memory bottleneck. However, the innate susceptibility to process, voltage and temperature (PVT) variations in effect restricts analog computing to ML inference applications of low to moderate complexity. In this work, we present a novel PVT variation tolerant SRAM based temporary memory (STEM) for analog in-memory computing. The proposed technique also allows unit cells to operate at ultralow currents, thereby enabling better energy efficiency. Monte Carlo simulations show that the proposed temporary memory array achieves a unit cell current variability (σ/μ) of 2% which is 5× better than that of conventional 8T unit cell. System level simulations of a 64 × 64 macro show that the proposed STEM achieves near baseline classification accuracy on FMNIST dataset using pre-trained weights, without chip-specific training.