A 12-bit 75 MS/s Asynchronous SAR ADC with Gain-Boosting Dynamic Comparator

This paper proposes a successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring a gain-boosting dynamic comparator design and a low-delay SAR logic. The proposed comparator incorporates positive feedback in the pre-amplifier, which enables high gain during the integration phase, thereby improving energy efficiency. Meanwhile, to ensure sufficient settling time for the internal capacitive digital-to-analog converter (CDAC), an asynchronous SAR logic with low logic delay in the SAR logic loop is implemented. Accordingly, a prototype ADC is manufactured using 28-nm CMOS technology, which achieves a power consumption of 860 μW at a 75 MHz sampling frequency. Moreover, the measured signal-to-noise and distortion ratio (SNDR) of the prototype at the Nyquist frequency is 60.9 dB, which translates to a Walden figure of merit (FOM
W
) of 12.7 fJ/conversion-step.