A 10T SRAM with Two Read and Write Modes across Row and Column for CAM Operation and Computing In-Memory

With SRAM-based computing in-memory (CIM), parallel searching is implemented through the multi-row activation scheme, which necessitates words to be stored in the column-wise fashion. However, existing column-wise write schemes usually require multi-cycle and cause write performance degradation for the SRAM with only row access transistors. In this study, we propose a novel 10T SRAM with both row and column access transistors, supporting data writing across row and column without additional data moving, overcoming the above problem. Furthermore, the proposed SRAM features horizontal and vertical read ports to enable two-direction logic operations, search operation, and matrix transposition, significantly enhancing computational flexibility. Besides, the array can be used to perform arithmetic operations. The 10T SRAM design is validated in a 4 Kb array with a 40-nm CMOS technology. It achieves a frequency of 917 MHz at 1.1V for logic operations. For binary content-addressable memory (BCAM) search operations, the energy consumption is 0.82 fJ/search/bit at 0.7 V in the worst case, and the frequency is up to 807 MHz at 1.1V.