A 0.4 V 180 nm CMOS Sub-μW Ultra-Compact and Low-Effort Design PWM-Based ADC

In this paper, a low-design effort, compact analog-to-digital converter (ADC) based on pulse-width modulation with a high level of digital (highly synthesizable) building block is described. Thus, the topology can take advantage of exploiting digital design tools offering supply-voltage scalability although relying on minimum re-design of the core block. The operating principle is based on the charge and discharge of a timing capacitor that allows an input-voltage-to-duty-cycle conversion. The duty cycle, in turn, enables the count of a counter exited by a ring oscillator. Post-layout time-domain simulations of the ADC performed at 180nm show a power consumption of 494 nW with a sample rate of 5 kS/s, 5.6 ENOB at 0.4 V supply voltage, and a compact area of 7200 μm
²
. The very low power consumption makes the proposed circuits very well suited for energy-harvested systems-on-chip for Internet of Things applications.