A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC

A fractional-N digital phase-locked loop (DPLL) utilizing a cyclic single-delay-pair Vernier time-to-digital converter (TDC) is introduced. By completely eliminating the quantization step mismatch of multiple delay cells in a traditional TDC chain/ring, and LFSR-dithering a MASH 11-1 modulated multi-modulus divider, the design can remarkably reduce fractional spurious tones and improve output clock jitter. Simulated in a 3nm FinFET process, the proposed DPLL consumes ~8.33mW from 0.875V supply @16GHz under a reference clock of 156.25MHz. The integrated jitter from 10kHz to 30MHz is ~596fsrms with the worst fractional spur of -65dBc, translated to a FoM of -235.3dB.