A 0.5 μm2 2-T Thin-Oxide OTP Antifuse with Reliability Enhanced by Auto Shut-off Program Logic for Low-Power Applications

A 2-T Antifuse cell with only thin-oxide transistors is proposed in this work, which is completely compatible with standard CMOS process. Its layout area is only as 0.5 μm
²
(1×0.5 μm
²
) in 40nm CMOS process, representing a 67% reduction in size compared with previous work at the same thickness. Considering the bitcell trade-off between area and reliability, the reliability is enhanced by an auto shut-off program logic and its feasibility is proven. Moreover, based on the cell, a 4Kb OTP array simulation shows that the program current is only 7 μA and read current is 5 μA. The characteristics of the memory array demonstrate its suitability for low-power applications in systems like RFID.