A Mixed-Signal Compute-in-Memory Architecture for Solving All-to-All Connected MAXCUT Problems with Sub-µs Time-to-Solution

Combinatorial and discrete optimization problems are prevalent in fields such as artificial intelligence, supply chain management, and wireless communications. The Ising machine, a quantum-inspired paradigm, offers a novel approach to accelerate these computations. However, realizing an Ising machine in an area/energy-efficient and scalable manner with low compute latency in CMOS is challenging. In this work, we propose a new mixed-signal SRAM-based compute-in-memory architecture to perform as a simulated bifurcation (SB) Ising machine. This realization leverages the inherent noise of analog computing, accelerating the time to anneal by injecting decaying noise in the analog domain. We have verified our solution and studied parameter optimization in the 180nm CMOS process with up to 60 spins using a post-layout co-simulation framework based on Synopsys PrimeSim. We benchmarked our design on 60-node random binary MAXCUT problems with all-to-all connections. This architecture achieves +95% of the ground state consistently over 10 graphs with < 1µs run time and 7.6mW average power.